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authorElyes HAOUAS <ehaouas@noos.fr>2019-10-25 14:05:17 +0200
committerMartin Roth <martinroth@google.com>2019-10-27 17:55:34 +0000
commit6df210b0c23b28bd3758fc8871b99752c9c825e9 (patch)
tree6b02034389ef3205306a57dd0ac59bb2bcd4b370 /src/mainboard/intel/d945gclf
parentede8dd0b9c0dcf1a2f1478e5cb4e035c148b9ed1 (diff)
downloadcoreboot-6df210b0c23b28bd3758fc8871b99752c9c825e9.tar.xz
mb/(ich7): Use macro instead of magic number
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f6fc8df2f4..f0ae18823e 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -69,12 +69,12 @@ static void early_ich7_init(void)
uint32_t reg32;
// program secondary mlt XXX byte?
- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
- reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
// usb transient disconnect
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);