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author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-22 20:36:58 +0100 |
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committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-12-03 21:02:12 +0100 |
commit | 4aad743434516d6c96f1afe21dd00b631e2c3692 (patch) | |
tree | f895dcff92712dd51af55fae3d71feeceb644e1b /src/mainboard/intel/d945gclf | |
parent | a234f45601e6e85a5179ec9cc446f070b86f425b (diff) | |
download | coreboot-4aad743434516d6c96f1afe21dd00b631e2c3692.tar.xz |
i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.
For compatibility with old bootblocks also enable it early in romstage.
Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
-rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4508968c46..4194a80aaa 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -89,9 +89,6 @@ static void rcba_config(void) /* Enable IOAPIC */ RCBA8(0x31ff) = 0x03; - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Disable unused devices */ //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; // RCBA32(0x3418) |= (1 << 0); // Required. |