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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-10 22:56:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-06-05 11:38:38 +0000 |
| commit | fbf380abac431b3b93ea180ee928b6b8f8dd8182 (patch) | |
| tree | 9daf9b6a870ff15a69cadef628a46fa4b353a4e7 /src/mainboard/intel/d945gclf | |
| parent | 06cfb21e243ec74660e4886cef2f2e9c6c755d9e (diff) | |
| download | coreboot-fbf380abac431b3b93ea180ee928b6b8f8dd8182.tar.xz | |
mb/*/devicetree.cb: Remove unavailable PCIe ports
Some variants only support 4 PCIe ports so there is no need to have
those unavailable ports in the devicetree.
Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
| -rw-r--r-- | src/mainboard/intel/d945gclf/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517fb90..716654c6eb 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/i945 device pci 1c.1 off end # PCIe port 2 device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI |