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authorAngel Pons <th3fanbus@gmail.com>2020-09-14 16:36:28 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-17 19:35:19 +0000
commitc8027454baeec2d18c06f537083ca30d3b70c1b0 (patch)
tree4f8ded82f2026d414c74092f0c85614d68b64ee8 /src/mainboard/intel/dcp847ske
parent92717ff3e475546366ac6439a4a0d4852bb2cb60 (diff)
downloadcoreboot-c8027454baeec2d18c06f537083ca30d3b70c1b0.tar.xz
nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree. The MCHBAR32 macro still needs a cast to preserve reproducibility. Only the native raminit path needs the cast, the MRC path does not. Tested with BUILD_TIMELESS=1, these boards remain identical: - Lenovo ThinkPad X230 - Dell OptiPlex 9010 - Roda RW11 (with MRC raminit) Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
-rw-r--r--src/mainboard/intel/dcp847ske/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index d793aca891..391d1f23b2 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -14,8 +14,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .mchbar = DEFAULT_MCHBAR,
+ .dmibar = DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,