diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/intel/dcp847ske | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/acpi/superio.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/dcp847ske/early_southbridge.c | 6 | ||||
| -rw-r--r-- | src/mainboard/intel/dcp847ske/romstage.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 8adc853c62..20c71a333b 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -19,7 +19,7 @@ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x4e -#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if !CONFIG(DISABLE_UART_ON_TESTPADS) #define NCT6776_SHOW_SP1 1 #endif #define NCT6776_SHOW_HWM 1 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 1a46f8bbab..510073540f 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -27,7 +27,7 @@ #include "superio.h" #include "thermal.h" -#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if CONFIG(DISABLE_UART_ON_TESTPADS) #define DEBUG_UART_EN 0 #else #define DEBUG_UART_EN COMA_LPC_EN @@ -46,7 +46,7 @@ void mainboard_rcba_config(void) /* Disable devices */ RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) /* Enable Gigabit Ethernet */ if (RCBA32(BUC) & PCH_DISABLE_GBE) { RCBA32(BUC) &= ~PCH_DISABLE_GBE; @@ -125,7 +125,7 @@ static const u16 superio_initvals[] = { SUPERIO_INITVAL(0x1a, 0x02), SUPERIO_INITVAL(0x1b, 0x6a), SUPERIO_INITVAL(0x27, 0x80), -#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#if CONFIG(DISABLE_UART_ON_TESTPADS) SUPERIO_INITVAL(0x2a, 0x80), #else SUPERIO_INITVAL(0x2a, 0x00), diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index ad31bba5ab..24ec912a4c 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -18,13 +18,13 @@ #include <stdint.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) #include <northbridge/intel/sandybridge/raminit_native.h> #else #include <northbridge/intel/sandybridge/raminit.h> #endif -#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { |