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authorArthur Heymans <arthur@aheymans.xyz>2019-06-16 23:36:28 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-16 14:08:29 +0000
commitd28d5071906e15c88939d889fbe40b117f5c303b (patch)
tree720d257987ba05695f2546b6fff0a180bde5b1b1 /src/mainboard/intel/dcp847ske
parenta06689c7e7d88f74fd1d12f8f5055b5ea7bc741f (diff)
downloadcoreboot-d28d5071906e15c88939d889fbe40b117f5c303b.tar.xz
sb/intel/bd82x6x/lpc: Set up default LPC decode ranges
This sets up some common default LPC decode ranges in a common place. This may set up more decode ranges than needed but that typically does not hurt. Mainboards needing additional ranges can do so in the mainboard pch_enable_lpc hook. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
-rw-r--r--src/mainboard/intel/dcp847ske/early_southbridge.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 705ace9bc6..984629574c 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,18 +27,8 @@
#include "superio.h"
#include "thermal.h"
-#if CONFIG(DISABLE_UART_ON_TESTPADS)
-#define DEBUG_UART_EN 0
-#else
-#define DEBUG_UART_EN COMA_LPC_EN
-#endif
-
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
- CNF2_LPC_EN | DEBUG_UART_EN);
- /* Decode SuperIO 0x0a00 */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
}
void mainboard_rcba_config(void)