mb/intel/dg41wv: Add mainboard

This board was used a test target for the x4x DDR3 raminit patches and
has an easy to access DIP8 socket.

What is tested and works:
* S3 resume
* PEG, PCI, USB, SATA
* Sound
* Ethernet
* Native graphic init (textmode and linear fb) on the VGA output
* Passing memtest86+ with 2 2Rx8 4G dimms
* PS2 Keyboard
* Flashing coreboot internally from vendor BIOS.

What does not work:
* Running dram at 533 MHz (limited at 400MHz currently)

Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux
4.10.

Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 43 insertions, 0 deletions

diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c
new file mode 100644
index 0000000000..23d566de96
--- /dev/null
+++ b/src/mainboard/intel/dg41wv/hda_verb.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	/* Realtek ALC662 rev1 */
+	0x10ec0662, /* Vendor ID */
+	0x80865756, /* Subsystem ID */
+	10, /* Number of entries */
+
+	/* Pin Widget Verb Table */
+
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);