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authorAngel Pons <th3fanbus@gmail.com>2020-11-03 00:03:32 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-23 09:55:43 +0000
commit2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 (patch)
tree3e4f0749bda60dd17635765faf47541eb59a4b1c /src/mainboard/intel/dg41wv
parent447233ce8c25863c2236d0b208bff7f63cd738fb (diff)
downloadcoreboot-2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2.tar.xz
mb/**/cmos.layout: Remove crusty comments
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
-rw-r--r--src/mainboard/intel/dg41wv/cmos.layout25
1 files changed, 0 insertions, 25 deletions
diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout
index b1f6e77558..cbf83229c9 100644
--- a/src/mainboard/intel/dg41wv/cmos.layout
+++ b/src/mainboard/intel/dg41wv/cmos.layout
@@ -4,50 +4,25 @@
entries
# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
0 120 r 0 reserved_memory
-#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
-#390 5 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
-#399 1 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: cpu
-#424 8 r 0 unused
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
-#435 549 r 0 unused
-
# coreboot config options: check sums
984 16 h 0 check_sum