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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-08 22:15:53 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-10 09:53:51 +0000
commitf5a57a883b6586c0e6dce9e6e34add09a96e647e (patch)
tree6b8cd82b302fe2d785c2f76a267f4e8e9c47f078 /src/mainboard/intel/dg41wv
parentab4eb2afc34266b53c6201bbca907dcb2ff07410 (diff)
downloadcoreboot-f5a57a883b6586c0e6dce9e6e34add09a96e647e.tar.xz
mb: Move timestamp_add_now to northbridge x4x
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index d1bf1bd1e4..d85c559c23 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -23,10 +23,8 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -100,12 +98,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);