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authorArthur Heymans <arthur@aheymans.xyz>2019-10-04 13:59:29 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-11 12:21:25 +0000
commit2437fe9dfab8e4056b633a39d51d07aa81ab3c9d (patch)
tree1dd071659a48c99c1e71ddf03b8cdf416da324c2 /src/mainboard/intel/dg41wv
parentcbe5357de02fa9f25ab9c0ca557e3057c701b059 (diff)
downloadcoreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.tar.xz
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 74f86221eb..81d50670e9 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -32,7 +32,6 @@
static void mb_lpc_setup(void)
{
- u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -55,10 +54,7 @@ static void mb_lpc_setup(void)
RCBA8(0x31ff) = 0x03;
RCBA8(0x31ff);
- reg32 = RCBA32(GCS);
- reg32 |= (1 << 5);
- RCBA32(GCS) = reg32;
- RCBA32(CG) = 0x00000001;
+ ich7_setup_cir();
}
static void ich7_enable_lpc(void)