mb/intel/dg43gt: Add mainboard

This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.

What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
  bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
  working gbe in this configuration though)
* USB.

What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
  BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)

Not tested:
* Sound;
* All the rest.

Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
  desoldering flash chip;
* In situ programming is not possible.

TESTED with SeaBIOS and Linux 4.10.8

Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 110 insertions, 0 deletions

diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
new file mode 100644
index 0000000000..6421673825
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -0,0 +1,110 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x		# CPU
+			device lapic 0xACAC off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		device pci 0.0 on end			# Host Bridge
+		device pci 2.0 on end			# Integrated graphics controller
+		device pci 2.1 on end			# Integrated graphics controller 2
+		device pci 3.0 off end		# ME
+		device pci 3.1 off end		# ME
+		chip southbridge/intel/i82801jx	# Southbridge
+			register "gpe0_en" = "0x40"
+
+			# Set AHCI mode.
+			register "sata_port_map"	= "0x1f"
+			register "sata_clock_request"	= "0"
+			register "sata_traffic_monitor"	= "0"
+
+			# Enable PCIe ports 0,2,3 as slots.
+			register "pcie_slot_implemented"	= "0xb"
+
+			device pci 19.0 on end		# GBE
+			device pci 1a.0 on end		# USB
+			device pci 1a.1 on end 		# USB
+			device pci 1a.2 on end 		# USB
+			device pci 1a.7 on end 		# USB
+			device pci 1b.0 on end		# Audio
+			device pci 1c.0 on end		# PCIe 1
+			device pci 1c.1 off end		# PCIe 2
+			device pci 1c.2 on end		# PCIe 3
+			device pci 1c.3 on end		# PCIe 4
+			device pci 1c.4 off end 	# PCIe 5
+			device pci 1c.5 off end 	# PCIe 6
+			device pci 1d.0 on end		# USB
+			device pci 1d.1 on end		# USB
+			device pci 1d.2 on end		# USB
+			device pci 1d.7 on end		# USB
+			device pci 1e.0 on end		# PCI bridge
+			device pci 1f.0 on		# ISA bridge
+				chip superio/winbond/w83627dhg	# Super I/O
+					device pnp 2e.0 on		# Floppy
+						# GLOBAL
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 on		# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 5
+						drq 0x74 = 4
+					end
+					device pnp 2e.2 on		# COM 1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM 2
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						irq 0x70 = 1
+						io 0x62 = 0x64
+						irq 0xf0 = 0x85
+					end
+					device pnp 2e.6 off end		# SPI
+					device pnp 2e.7 on		# GPIO 6
+						irq 0x30 = 0x06
+					end
+					device pnp 2e.8 off end		# WDTO# PLED
+					device pnp 2e.9 on		# GPIO 2,3,4,5
+						irq 0x30 = 0x0a
+					end
+					device pnp 2e.a on		# ACPI
+						irq 0xe4 = 0x30 # power dram during S3
+					end
+					device pnp 2e.b on		# Hardware monitor
+						io 0x60 = 0x290
+					end
+					device pnp 2e.c off end		# PECI, SST
+				end
+			end
+			device pci 1f.1 on end		# PATA/IDE
+			device pci 1f.2 on end		# SATA
+			device pci 1f.3 on end		# SMbus
+			device pci 1f.4 off end
+			device pci 1f.5 on end		# IDE
+			device pci 1f.6 off end
+		end
+	end
+end