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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-07 17:05:57 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-12 22:22:27 +0000 |
| commit | e4188a23dde8db7f1386f3f782b8a43c40811119 (patch) | |
| tree | 295ba6c0b04b19390380c09e31aaa27007110369 /src/mainboard/intel/dg43gt/devicetree.cb | |
| parent | 33863b6eff270a1eb57defb8081654b3df2b49df (diff) | |
| download | coreboot-e4188a23dde8db7f1386f3f782b8a43c40811119.tar.xz | |
mb/intel/dg43gt: Configure clockgen
This makes the VGA output on the DVI-I connector usable.
This reuses vendor settings.
Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel/dg43gt/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/dg43gt/devicetree.cb | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 6421673825..79a8eb7309 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -101,7 +101,19 @@ chip northbridge/intel/x4x # Northbridge end device pci 1f.1 on end # PATA/IDE device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMbus + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 # SLG8XP549T + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff }" + register "regs" = "{ 0x11, 0xd9, 0xff, + 0xfd, 0xff, 0x00, 0x00, + 0x06, 0x10, 0x05, 0x01, + 0x80, 0x0d }" + device i2c 69 on end + end + end device pci 1f.4 off end device pci 1f.5 on end # IDE device pci 1f.6 off end |