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| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2020-09-03 07:08:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:30:44 +0000 |
| commit | aab188174f7fa349ef395ecb38a41d5b6cf45e92 (patch) | |
| tree | 4c2e25753bed32087765353c7f80ac781218c5f4 /src/mainboard/intel/dg43gt | |
| parent | b369dde9b1cc9daffce83dc809101e0fd0a0e346 (diff) | |
| download | coreboot-aab188174f7fa349ef395ecb38a41d5b6cf45e92.tar.xz | |
soc/intel/elkhartlake: Update SA & PM related definitions
1. Update SA base address & size
2. Update GBE control bit register value
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/dg43gt')
0 files changed, 0 insertions, 0 deletions