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authorStefan Reinauer <reinauer@chromium.org>2012-04-30 16:42:07 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-05-01 20:08:00 +0200
commit816d081760d4cccf0db0c952728f5ec6926d6c85 (patch)
tree12542d99189f5b412ad39fb25a78427dcfb4aaa5 /src/mainboard/intel/eagleheights
parent8508cff0359dcd99d319407f15e5034ff896a716 (diff)
downloadcoreboot-816d081760d4cccf0db0c952728f5ec6926d6c85.tar.xz
Fix SATA port map to only enable port 0
The sata controller comes up in legacy/normal mode and is currently put into AHCI mode in romstage. If that is removed and the controller is left alone until the ramstage driver (like we do on Stumpy/Lumpy) then the resource allocator will have configured the device for IDE mode with an IO address in BAR5. Then when the ramstage driver puts the controller into AHCI mode it will not have the correct resources to do the rest of the AHCI setup. So the controller mode needs to be changed in the enable stage rather than in the init phase. This same register contains the port map and it is a R/WO (write once) field so the configured port map must be written at the same time. For non-AHCI mode the devicetree map was ignored before but it is used now. Since the port map register is now written at enable step it does not need to be written again during init. With this change the sata port map can be reduced to just port 0 and then U-boot does not have to probe all available ports. Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/977 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/eagleheights')
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