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| author | Nico Huber <nico.huber@secunet.com> | 2012-10-01 15:53:14 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-01 22:21:12 +0100 |
| commit | 41392df0d1e22aeaa694d5e8b6f58db198da423c (patch) | |
| tree | 990601d2dd38d87f43d340c8113f5acc8d53a130 /src/mainboard/intel/eagleheights | |
| parent | bef3d347e8a21049d72407246a5d4ec1339b5601 (diff) | |
| download | coreboot-41392df0d1e22aeaa694d5e8b6f58db198da423c.tar.xz | |
Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
We had only some MSR definitions in there, which are used in speedstep
related code. I think speedstep.h is the better and less confusing place
for these.
Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1655
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/eagleheights')
| -rw-r--r-- | src/mainboard/intel/eagleheights/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index a250c05c6b..1e906efdcb 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -30,7 +30,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <cpu/intel/acpi.h> +#include <cpu/intel/speedstep.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "reset.c" |