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| author | Hung-Te Lin <hungte@chromium.org> | 2013-03-01 10:34:04 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-01 06:53:57 +0100 |
| commit | f12e56181788387c560c9b8d0f3d61fce4a4333a (patch) | |
| tree | b136e09de17cf327df097e2cef0b9da539d42c73 /src/mainboard/intel/eagleheights | |
| parent | 27bd64a8be3b4e3bff883377e3a0f5ae55d176c7 (diff) | |
| download | coreboot-f12e56181788387c560c9b8d0f3d61fce4a4333a.tar.xz | |
armv7/snow: Add S5P MSHC initialization in ROM stage.
The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and
pinmux settings before it can be detected and used in ramstage / payload.
Verified on armv7/snow and successfully boot into ramstage.
Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2561
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/eagleheights')
0 files changed, 0 insertions, 0 deletions