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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-27 23:16:30 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-30 23:08:06 +0200 |
commit | 6651da3bcd51ad6ea918c21564eb505b76c8c7aa (patch) | |
tree | 7a10210115d4e600f7f6c16ddd6c61395acf8efb /src/mainboard/intel/emeraldlake2/acpi/superio.asl | |
parent | c31384e62c98baf2fb847d55bb31a82f492ce265 (diff) | |
download | coreboot-6651da3bcd51ad6ea918c21564eb505b76c8c7aa.tar.xz |
Add support for Intel Emerald Lake 2 CRB
This adds support for Intel's Emerald Lake 2 board.
Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/951
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2/acpi/superio.asl')
-rw-r--r-- | src/mainboard/intel/emeraldlake2/acpi/superio.asl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl new file mode 100644 index 0000000000..f803aaf8b9 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "../../../../superio/smsc/sio1007/acpi/superio.asl" |