diff options
| author | Gabe Black <gabeblack@google.com> | 2012-03-29 18:04:56 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 19:33:58 +0200 |
| commit | f40a2590acf4db45fa89098b9e406e45ffaffc0c (patch) | |
| tree | d8aa31447dae2f26e53ddcbf4aecc031d6565537 /src/mainboard/intel/emeraldlake2/acpi | |
| parent | e6063fee5c954d5acd80fd51e11aeac31e83d13d (diff) | |
| download | coreboot-f40a2590acf4db45fa89098b9e406e45ffaffc0c.tar.xz | |
Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.
The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
any actual developer mode, recovery mode, or write protect switches, let alone
GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
which are for other things but which aren't used by hardware or, for instance,
the EC to do something Coreboot doesn't control.
The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
schematic. The name is at least very reminiscent of the right thing even if
it's supposed to be used for something else. There's a jumper on the board
labelled J8G1 which can force the line to ground, and if not, there's a switch
on the front of the case which toggles its value. "RECOVER" is for recovery
mode and "KEEP" is for normal mode.
The developer mode switch is connected to GPIO 57 and is called SV_DET on the
schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
I can tell, can't be controlled in any other way. When the jumper is in place
and the pins are shorted, developer mode is selected. When the jumper is
removed, normal mode is selected.
The write protect is connected to GPIO 48 which is called BIOS_RESP on the
schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to
be the only way to control the line it's on. When the jumper is in place,
write protect is "disabled", and when it's in place it's "enabled" even though
there's no functional difference.
The input for the recovery mode switch was chosen because of the name it
already had on the CRB, BIOS recovery, and because there's a switch to control
it on the front of the case which makes it easy to get at. The jumpers for
developer mode and recovery mode were chosen because there weren't very many
options available, and of those these were next to each other which should
make them easier to find and work with. It might be a good idea to wire toggle
switches up to the pins of those jumpers so they'll be easy to identify, can
be labelled, and would be easier to work with than little jumpers in the
middle of the motherboard.
Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2/acpi')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl index 65202cb6d4..81ead2e554 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl @@ -65,9 +65,9 @@ Device (CRHW) Method(GPIO, 0, Serialized) { Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect + Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch + Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect Package() { 0x100, 0, 9, "CougarPoint" }, // debug header gpio Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1 Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2 |