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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
| commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
| tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/intel/emeraldlake2 | |
| parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) | |
| download | coreboot-fa5d0f835b1f3bb8907e616913cbf7b91d09ef26.tar.xz | |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/early_init.c (renamed from src/mainboard/intel/emeraldlake2/romstage.c) | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 974241dcc2..3e78db075b 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -17,3 +17,5 @@ romstage-y += chromeos.c ramstage-y += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2cfb5569fb..94a46550b2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -43,7 +44,7 @@ void mainboard_pch_lpc_setup(void) } } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; const u16 runtime_port = 0x180; |