diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 00:41:10 +0100 |
---|---|---|
committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 01:28:57 +0100 |
commit | 48b69aca47c7bd2dff6298e936904eae7bdd5271 (patch) | |
tree | 1ff06d986042158c3d37f7383f35dfee51e13192 /src/mainboard/intel/galileo/gen1.h | |
parent | 5fae8294104ae62353466298fae493e717056a28 (diff) | |
download | coreboot-48b69aca47c7bd2dff6298e936904eae7bdd5271.tar.xz |
Revert "mainboard/intel/galileo: Add vboot support"
This reverts commit a50ced2eba20a007fa5b486c251c252ad09868cf.
Change-Id: I4f7d3177015bfe280111843014c310e0d333cb17
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18814
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/galileo/gen1.h')
-rw-r--r-- | src/mainboard/intel/galileo/gen1.h | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h index 524daf8f67..23b23091d2 100644 --- a/src/mainboard/intel/galileo/gen1.h +++ b/src/mainboard/intel/galileo/gen1.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corp. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -150,29 +150,3 @@ static const struct reg_script gen1_i2c_0x21_init[] = { REG_SCRIPT_END }; - -static const struct reg_script gen1_tpm_reset_0x20[] = { - /* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1): - * low, output, delay, input - */ - REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT5, ~BIT1), - REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5), - REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT1), - TIME_DELAY_USEC(5), - REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1), - - REG_SCRIPT_END -}; - -static const struct reg_script gen1_tpm_reset_0x21[] = { - /* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1): - * low, output, delay, input - */ - REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT5, ~BIT1), - REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5), - REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT1), - TIME_DELAY_USEC(5), - REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1), - - REG_SCRIPT_END -}; |