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author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-26 10:06:42 -0800 |
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committer | Martin Roth <martinroth@google.com> | 2016-02-04 19:20:06 +0100 |
commit | 93dd5f78ffc7d9f9311866c38afc78062c6a52ef (patch) | |
tree | 05b81477ef8ef3e4009861fd390af50b5ee635da /src/mainboard/intel/galileo/romstage.c | |
parent | 4af905ac95685500e71fb32cf5cec430d1a75447 (diff) | |
download | coreboot-93dd5f78ffc7d9f9311866c38afc78062c6a52ef.tar.xz |
mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a
minimal coreboot image. Please note that this configuration does not
run. Include HTML documentation for the Galileo Gen 2 board.
Testing is successful if build completes successfully.
TEST=Build for Galileo
Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/galileo/romstage.c')
-rw-r--r-- | src/mainboard/intel/galileo/romstage.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100644 index 0000000000..dfae772580 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} |