mainboard/intel/glkrvp: Add support for GLKRVP

GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1

GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)

By default, CONFIG_GLK_CHROME_EC is selected for  external ChromeEC AIC
config.

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 54 insertions, 0 deletions

diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd
new file mode 100644
index 0000000000..56c8d58f08
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/chromeos.fmd
@@ -0,0 +1,54 @@
+FLASH 16M {
+	WP_RO@0x0 0x400000 {
+		SI_DESC@0x0 0x1000
+		IFWI@0x1000 0x1ff000
+		RO_VPD@0x200000 0x4000
+		RO_SECTION@0x204000 0x1fc000 {
+			FMAP@0x0 0x800
+			RO_FRID@0x800 0x40
+			RO_FRID_PAD@0x840 0x7c0
+			COREBOOT(CBFS)@0x1000 0x19b000
+			GBB@0x19c000 0x40000
+			RO_UNUSED@0x1dc000 0x20000
+		}
+	}
+	MISC_RW@0x400000 0x4a000 {
+        UNIFIED_MRC_CACHE@0x0 0x31000 {
+            RECOVERY_MRC_CACHE@0x0 0x10000
+            RW_MRC_CACHE@0x10000 0x20000
+            RW_VAR_MRC_CACHE@0x30000 0x1000
+        }
+		RW_ELOG@0x31000 0x4000
+		RW_SHARED@0x35000 0x4000 {
+			SHARED_DATA@0x0 0x2000
+			VBLOCK_DEV@0x2000 0x2000
+		}
+		RW_VPD@0x39000 0x2000
+		TMP_UNUSED_HOLE@0x3B000 0xF000
+	}
+	RW_SECTION_A@0x44a000 0x477800 {
+		VBLOCK_A@0x0 0x10000
+		FW_MAIN_A(CBFS)@0x10000 0x4677c0
+		RW_FWID_A@0x4777c0 0x40
+	}
+	RW_SECTION_B@0x8c1800 0x477800 {
+		VBLOCK_B@0x0 0x10000
+		FW_MAIN_B(CBFS)@0x10000 0x4677c0
+		RW_FWID_B@0x4777c0 0x40
+	}
+	RW_NVRAM@0xd39000 0x6000
+	RW_LEGACY(CBFS)@0xd3f000 0x200000
+	BIOS_UNUSABLE@0xf3f000 0x40000
+	DEVICE_EXTENSION@0xf7f000 0x80000
+	# Currently, it is required that the BIOS region be a multiple of 8KiB.
+	# This is required so that the recovery mechanism can find SIGN_CSE
+	# region aligned to 4K at the center of BIOS region. Since the
+	# descriptor at the beginning uses 4K and BIOS starts at an offset of
+	# 4K, a hole of 4K is created towards the end of the flash to compensate
+	# for the size requirement of BIOS region.
+	# FIT tool thus creates descriptor with following regions:
+	# Descriptor --> 0 to 4K
+	# BIOS       --> 4K to 0xf7f000
+	# Device ext --> 0xf7f000 to 0xfff000
+	UNUSED_HOLE@0xfff000 0x1000
+}