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| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-10-26 16:58:05 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-04 00:40:38 +0000 |
| commit | f08ed7d790ade3f29680dc300b71cf95a694ce2a (patch) | |
| tree | 03c761aaf0b75260d0f44adaae43fc5be3ea29eb /src/mainboard/intel/glkrvp | |
| parent | 96939ae694dc2b294ca04129c6ec88ef3f5d8809 (diff) | |
| download | coreboot-f08ed7d790ade3f29680dc300b71cf95a694ce2a.tar.xz | |
src/mainboard/glkrvp: Fix ec_in_rw and wp
Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/glkrvp')
| -rw-r--r-- | src/mainboard/intel/glkrvp/chromeos.c | 6 | ||||
| -rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/gpio.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h | 4 |
3 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index b1429b6286..b7f56ec53d 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -30,8 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -71,8 +70,7 @@ int clear_recovery_mode_switch(void) int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + return 0; } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index bf70e11e9a..f8ab6fd6bb 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -284,8 +284,8 @@ variant_sleep_gpio_table(size_t *num) static const struct cros_gpio cros_gpios[] = { #if 0 - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), #endif }; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index 91a1c038e0..41de87c7ce 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -29,10 +29,6 @@ #define GPE_EC_WAKE GPE0_DW1_06 -/* Write Protect and indication if EC is in RW code. */ -#define GPIO_PCH_WP GPIO_75 -#define GPIO_EC_IN_RW GPIO_41 - /* Memory SKU GPIOs. */ #define MEM_CONFIG3 GPIO_45 #define MEM_CONFIG2 GPIO_38 |