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authorMariusz Szafranski <mariuszx.szafranski@intel.com>2017-08-02 18:51:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2017-09-05 13:39:58 +0000
commitfaf7a8e8592f47dc9c92ab1672e30bbf60bc3581 (patch)
tree4f6ebc18f3c988eb6c52ba8e857c211d36c11651 /src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
parenta404133547c98094a326f60b83e1576ba94b8c06 (diff)
downloadcoreboot-faf7a8e8592f47dc9c92ab1672e30bbf60bc3581.tar.xz
mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC ("Denverton" and "Denverton-NS") for the communications segment/market. The MohonPeak coreboot was used as the starting template with additions/modifications from other Intel Apollo Lake/Skylake coreboot. Tested with TianoCore payload (UDK2015) and Poky (Yocto Project Reference Distro) 2.0 with kernel 4.1.8 booted from SATA drive and external USB pendrive. Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex')
-rw-r--r--src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex513
1 files changed, 513 insertions, 0 deletions
diff --git a/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex b/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
new file mode 100644
index 0000000000..4abad8dd32
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
@@ -0,0 +1,513 @@
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