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author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-05 18:11:19 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 10:01:21 +0000 |
commit | 351e3e520ba71b4aafaf930af37f78b71c1d7251 (patch) | |
tree | eb872d8fb0aaefad7b313e9dd5e31fe1e7cf3242 /src/mainboard/intel/icelake_rvp/romstage_fsp_params.c | |
parent | 20eaef024cb06677de10d018e6f70c28d1841290 (diff) | |
download | coreboot-351e3e520ba71b4aafaf930af37f78b71c1d7251.tar.xz |
src: Use include <console/console.h> when appropriate
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/mainboard/intel/icelake_rvp/romstage_fsp_params.c')
-rw-r--r-- | src/mainboard/intel/icelake_rvp/romstage_fsp_params.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index dd33021ae5..b9ce3941f4 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -14,12 +14,12 @@ */ #include <arch/byteorder.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> -#include "spd/spd.h" #include <spd_bin.h> +#include "spd/spd.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { } |