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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-11-13 14:52:04 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-16 01:13:10 +0100 |
| commit | fa2fc339c51649b106bf78703cbc17694abcee23 (patch) | |
| tree | 2060aa4f53a88cb2dd269a83f3f02e16f45ca00a /src/mainboard/intel/jarrell | |
| parent | 55db955bcdad90c9ebd8b755ae417234d46d731a (diff) | |
| download | coreboot-fa2fc339c51649b106bf78703cbc17694abcee23.tar.xz | |
Drop Kconfig variable BOARD_HAS_HARD_RESET
hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.
Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/intel/jarrell')
| -rw-r--r-- | src/mainboard/intel/jarrell/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/jarrell/power_reset_check.c | 10 | ||||
| -rw-r--r-- | src/mainboard/intel/jarrell/reset.c | 31 | ||||
| -rw-r--r-- | src/mainboard/intel/jarrell/romstage.c | 2 |
4 files changed, 11 insertions, 33 deletions
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index a3c34f44b9..2a62777449 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 select ROMCC - select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c index 567d15c10f..0ac526f0ee 100644 --- a/src/mainboard/intel/jarrell/power_reset_check.c +++ b/src/mainboard/intel/jarrell/power_reset_check.c @@ -1,3 +1,13 @@ +void full_reset(void) +{ + /* Enable power on after power fail... */ + unsigned byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + byte &= 0xfe; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte); + + outb(0x0e, 0xcf9); +} static void power_down_reset_check(void) { diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c deleted file mode 100644 index 2ecfa48b8f..0000000000 --- a/src/mainboard/intel/jarrell/reset.c +++ /dev/null @@ -1,31 +0,0 @@ -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <reset.h> - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} - -#ifndef __ROMCC__ -/* Used only board-internally by power_reset_check.c and jarell_fixups.c */ -void full_reset(void); -#endif - -void full_reset(void) -{ - /* Enable power on after power fail... */ - unsigned byte; - byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - byte &= 0xfe; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte); - - outb(0x0e, 0xcf9); -} - diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 3eff025968..784e7df3e6 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -12,7 +12,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "watchdog.c" -#include "reset.c" +#include "southbridge/intel/i82801ex/reset.c" #include "power_reset_check.c" #include "jarrell_fixups.c" #include "superio/nsc/pc87427/early_init.c" |