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authorUwe Hermann <uwe@hermann-uwe.de>2006-10-27 11:38:22 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2006-10-27 11:38:22 +0000
commit586470c646ac1b8753858b013b268f049a28b818 (patch)
treee701bc449d20bf89c784194f34ffd3c4a11bc8eb /src/mainboard/intel/jarrell
parente0e1d425274d5e2c90e19eec6ef125d1fffd73a1 (diff)
downloadcoreboot-586470c646ac1b8753858b013b268f049a28b818.tar.xz
Rename E7520 to e7520, and E7525 to e7525 in the code. The next commit
will then rename the E7520 and E7525 directories respectively. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/jarrell')
-rw-r--r--src/mainboard/intel/jarrell/Config.lb2
-rw-r--r--src/mainboard/intel/jarrell/auto.c6
-rw-r--r--src/mainboard/intel/jarrell/failover.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
index c355640cc1..69795b0026 100644
--- a/src/mainboard/intel/jarrell/Config.lb
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
dir /pc80
config chip.h
-chip northbridge/intel/E7520
+chip northbridge/intel/e7520
device pci_domain 0 on
device pci 00.0 on end
device pci 00.1 on end
diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c
index f102746636..d5e68e2343 100644
--- a/src/mainboard/intel/jarrell/auto.c
+++ b/src/mainboard/intel/jarrell/auto.c
@@ -11,7 +11,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
#include "power_reset_check.c"
#include "jarrell_fixups.c"
#include "superio/nsc/pc87427/pc87427_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#define SIO_GPIO_BASE 0x680
@@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
#include "sdram/generic_sdram.c"
#include "debug.c"
diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c
index 5029d98611..c5f3f8089d 100644
--- a/src/mainboard/intel/jarrell/failover.c
+++ b/src/mainboard/intel/jarrell/failover.c
@@ -9,7 +9,7 @@
#include "arch/i386/lib/console.c"
#include "pc80/mc146818rtc_early.c"
#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
static unsigned long main(unsigned long bist)
{