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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
commitabf2ad716daff751d75907d47bcae4a7044fd7b4 (patch)
treef82427b43d76a4791253373affed1af8669e2e7b /src/mainboard/intel/jarrell
parent389240f288b2708617a35ebe8d7f89b3bff316c5 (diff)
downloadcoreboot-abf2ad716daff751d75907d47bcae4a7044fd7b4.tar.xz
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/jarrell')
-rw-r--r--src/mainboard/intel/jarrell/Config.lb182
-rw-r--r--src/mainboard/intel/jarrell/Options.lb242
2 files changed, 0 insertions, 424 deletions
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
deleted file mode 100644
index 722ba4027b..0000000000
--- a/src/mainboard/intel/jarrell/Config.lb
+++ /dev/null
@@ -1,182 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520
- device pci_domain 0 on
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 01.0 on end
- device pci 02.0 on
- chip southbridge/intel/pxhd # pxhd1
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 00.2 on
- chip drivers/generic/generic
- device pci 04.0 on end
- device pci 04.1 on end
- end
- end
- device pci 00.3 on end
- end
- end
- device pci 06.0 on end
- chip southbridge/intel/i82801er # i82801er
- device pci 1d.0 on end
- device pci 1d.1 on end
- device pci 1d.2 on end
- device pci 1d.3 off end
- device pci 1d.7 on end
- device pci 1e.0 on
- chip drivers/ati/ragexl
- device pci 0c.0 on end
- end
- end
- device pci 1f.0 on
- chip superio/nsc/pc87427
- device pnp 2e.0 off end
- device pnp 2e.2 on
-# io 0x60 = 0x2f8
-# irq 0x70 = 3
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on
-# io 0x60 = 0x3f8
-# irq 0x70 = 4
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.4 off end
- device pnp 2e.5 off end
- device pnp 2e.6 on
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.7 off end
- device pnp 2e.9 off end
- device pnp 2e.a off end
- device pnp 2e.f on end
- device pnp 2e.10 off end
- device pnp 2e.14 off end
- end
- end
- device pci 1f.1 on end
- device pci 1f.2 off end
- device pci 1f.3 on end
- device pci 1f.5 off end
- device pci 1f.6 off end
- register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
- register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
- register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
- end
- end
- device apic_cluster 0 on
- chip cpu/intel/socket_mPGA604 # cpu 0
- device apic 0 on end
- end
- chip cpu/intel/socket_mPGA604 # cpu 1
- device apic 6 on end
- end
- end
-end
diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb
deleted file mode 100644
index 91927eee0d..0000000000
--- a/src/mainboard/intel/jarrell/Options.lb
+++ /dev/null
@@ -1,242 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-uses CONFIG_MAX_REBOOT_CNT
-uses CONFIG_USE_WATCHDOG_ON_BOOT
-
-
-###
-### Build options
-###
-
-##
-## Because we do the stutter start we need more attempts
-##
-default CONFIG_MAX_REBOOT_CNT=8
-
-##
-## Use the watchdog to break out of a lockup condition
-##
-default CONFIG_USE_WATCHDOG_ON_BOOT=1
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=2097152
-
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=18
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
-default CONFIG_MAINBOARD_VENDOR= "Intel"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
-#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## CONFIG_DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end