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| author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-07-06 21:05:04 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-07-06 21:05:04 +0000 |
| commit | eb50c7d922e91f0247b3705eccb2d2eec638c277 (patch) | |
| tree | 2def570d089b2f6deb2beac165e18756a578e308 /src/mainboard/intel/jarrell | |
| parent | 8376831eafc1be1175529fd21e0d2fe40339d4eb (diff) | |
| download | coreboot-eb50c7d922e91f0247b3705eccb2d2eec638c277.tar.xz | |
Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/jarrell')
| -rw-r--r-- | src/mainboard/intel/jarrell/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/jarrell/romstage.c | 3 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index e5d5314f97..aef112c9ba 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -9,6 +9,7 @@ config BOARD_INTEL_JARRELL select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index b6e74fac08..1caf4b9548 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -5,8 +5,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" |