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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-08-11 18:28:29 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-08-24 14:05:35 +0000
commitf5b3a49b76e3feeb617c51df432d36bdb043a0ce (patch)
tree856b1d18046924f39985eb4a346eb1e25928999d /src/mainboard/intel/jasperlake_rvp
parentbf4e71e1b3412d3fc864f6b1e4eda22f60c6d47d (diff)
downloadcoreboot-f5b3a49b76e3feeb617c51df432d36bdb043a0ce.tar.xz
mb/intel/jslrvp: Correct PCI root port mapping
Jasper Lake SoC had PCI root port mapping swap, thats why we were using swapped mapping earlier for all the boards Recently, patch was pushed to handle this swap in PCI enumeration code for Jasper Lake and we need to correct this mapping. Now this mapping aligns with actual port mapping in the schematics BUG=None BRANCH=None TEST=NVMe and WLAN are getting detected after this changes Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index c5a3fc30bc..268d239c06 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -416,12 +416,12 @@ chip soc/intel/jasperlake
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 on end # PCI Express Port 2 - WLAN
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.4 on end # PCI Express Port 5 - NVMe
+ device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1e.0 on end # UART #0