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| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-11-06 14:05:35 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-07 20:53:54 +0100 |
| commit | dd397f0971c140e3a5b80eb0c568384c154a60e6 (patch) | |
| tree | d2565123c1c1947ed5947bb57772ccca1451c22c /src/mainboard/intel/kblrvp/acpi | |
| parent | bc6a3890499a7459d0592a872334a09d0514d78b (diff) | |
| download | coreboot-dd397f0971c140e3a5b80eb0c568384c154a60e6.tar.xz | |
mainboard/intel/kblrvp: Add Chrome EC switch
Add Chrome EC switch to enable building with/without Chrome EC.
Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17248
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/kblrvp/acpi')
| -rw-r--r-- | src/mainboard/intel/kblrvp/acpi/ec.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 2203e2f7f0..7d7ff2ffa8 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,6 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE - +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> +#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 1b8fe431e6..5d2b3071b5 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include "../gpio.h" +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (LID0) @@ -34,6 +35,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) } } +#endif /* * LPC Trusted Platform Module |