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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2016-11-29 16:51:08 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-12-03 02:34:53 +0100 |
| commit | 2ed14f61d1a2976d0ebce59fcc67bd61fce4100d (patch) | |
| tree | 7f179c8e6c233e7771a6d721df1763cbdef12ead /src/mainboard/intel/kblrvp/romstage.c | |
| parent | d9e654321c5a063898f39aa64898fac26a6fd23f (diff) | |
| download | coreboot-2ed14f61d1a2976d0ebce59fcc67bd61fce4100d.tar.xz | |
mainboard/intel/kblrvp: Enabling Kaby Lake RVP7
Add support for Kaby Lake RVP7 board
* Add RVP7 board support in Kconfig
* Override default descriptor and ME binary paths in Kconfig
since those binaries will differ for RVP3 and RVP7
* Add RVP7 board name in board_info.txt and Kconfig.name
* Add devicetree.cb for RVP7 in the variants path
* Add gpio.h for RVP7 in variants/include/variant path
* Made board specific code for retrieving spd, i.e., in RVP7
there is non-soldered DIMMs, so SPD is read through smbus,
unlike RVP3 where memory DIMMs are soldered down with board.
Hence for RVP3, the spd binaries will be fixed and can be
kept as binary file in cbfs.
BUG=none
BRANCH=none
TEST=Built and boot Kaby Lake RVP7
Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/romstage.c')
| -rw-r--r-- | src/mainboard/intel/kblrvp/romstage.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index bc39a806da..2e0292daf7 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -31,7 +31,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - struct region_device spd_rdev; u8 spd_index = (get_board_id() >> 5) & 0x7; printk(BIOS_INFO, "SPD index %d\n", spd_index); @@ -41,15 +40,22 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - /* RVP3 SPD */ - mem_cfg->DqPinsInterleaved = 0; - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { - die("spd.bin not found\n"); + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + struct region_device spd_rdev; + + mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ + struct spd_block blk; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; } - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } |