mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3

Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.

Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.

* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.

This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.

Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 42 insertions, 0 deletions

diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
new file mode 100644
index 0000000000..d4fd1131f7
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <soc/romstage.h>
+#include <soc/gpio.h>
+#include "spd/spd.h"
+#include <string.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = 0;
+	mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
+	if (mainboard_has_dual_channel_mem())
+		mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+	mem_cfg->MemorySpdDataLen = SPD_LEN;
+}