diff options
author | Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2019-01-04 01:10:25 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 10:01:25 +0000 |
commit | 7e48b47185d72e9a0c6bee5bab352d3c819dafe4 (patch) | |
tree | 80563a9d6a8149f85f6796cf2ab6948ecf271a92 /src/mainboard/intel/kblrvp/variants/rvp7 | |
parent | e81880dd0d188867b4fb4d1d89584d5e2026c041 (diff) | |
download | coreboot-7e48b47185d72e9a0c6bee5bab352d3c819dafe4.tar.xz |
mb/intel/kblrvp: Enable overridetree support for variants
This patch add devicetree.cb in baseboard and overridetree.cb
for RVP3, RVP7 and RVP8 variants.
BUG= None
TEST= build with BUILD_TIMELESS=1, static.c remains same on before &
after enabling overridetree.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ib7d492e2a92aed10ad0426d57640d0ed56733847
Reviewed-on: https://review.coreboot.org/c/30623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp7')
-rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb (renamed from src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb) | 88 |
1 files changed, 0 insertions, 88 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index efcf9be3b8..abd9886d17 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -9,63 +9,14 @@ chip soc/intel/skylake # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s - register "PmConfigSlpS3MinAssert" = "0x02" - - # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s - register "PmConfigSlpS4MinAssert" = "0x04" - - # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s - register "PmConfigSlpSusMinAssert" = "0x03" - - # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s - register "PmConfigSlpAMinAssert" = "0x03" - - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -199,11 +150,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # Enable/Disable VMX feature - register "VmxEnable" = "0" # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G5" @@ -217,53 +164,18 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 on end # PCI Express Port 3 device pci 1c.3 on end # PCI Express Port 4 device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end end end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE end end |