soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 21 insertions, 1 deletions

diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index 0d2bd0f397..a8e835e95c 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -138,16 +138,22 @@ chip soc/intel/skylake
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpClkReqSupport[0]" = "1"
 	register "PcieRpClkReqNumber[0]" = "2"
+	# RP1, uses uses CLK SRC 2
+	register "PcieRpClkSrcNumber[0]" = "2"
 
 	# PCIE Port 5 x1 -> SLOT2/LAN
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpClkReqSupport[4]" = "1"
 	register "PcieRpClkReqNumber[4]" = "3"
+	# RP5, uses uses CLK SRC 3
+	register "PcieRpClkSrcNumber[4]" = "3"
 
 	# PCIE Port 6 x1 -> SLOT3
 	register "PcieRpEnable[5]" = "1"
 	register "PcieRpClkReqSupport[5]" = "1"
 	register "PcieRpClkReqNumber[5]" = "1"
+	# RP6, uses uses CLK SRC 1
+	register "PcieRpClkSrcNumber[5]" = "1"
 
 	# PCIE Port 7 Disabled
 	# PCIE Port 8 Disabled
@@ -155,11 +161,15 @@ chip soc/intel/skylake
 	register "PcieRpEnable[8]" = "1"
 	register "PcieRpClkReqSupport[8]" = "1"
 	register "PcieRpClkReqNumber[8]" = "5"
+	# RP9, uses uses CLK SRC 5
+	register "PcieRpClkSrcNumber[8]" = "5"
 
 	# PCIE Port 10 x1 -> WiGig
 	register "PcieRpEnable[9]" = "1"
 	register "PcieRpClkReqSupport[9]" = "1"
 	register "PcieRpClkReqNumber[9]" = "4"
+	# RP10, uses uses CLK SRC 4
+	register "PcieRpClkSrcNumber[9]" = "4"
 
 	# USB 2.0 Enable all ports
 	register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)"		# TYPE-A Port
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
index 6f45a46a7d..5c41f22d8a 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
@@ -148,13 +148,23 @@ chip soc/intel/skylake
 	register "PcieRpClkReqSupport[5]" = "1"
 	register "PcieRpClkReqSupport[8]" = "1"
 
-	# RP 9 uses SRCCLKREQ5#
+	# RP 3 uses SRCCLKREQ5#
 	register "PcieRpClkReqNumber[2]" = "5"
 	register "PcieRpClkReqNumber[3]" = "2"
 	register "PcieRpClkReqNumber[4]" = "3"
 	register "PcieRpClkReqNumber[5]" = "4"
 	register "PcieRpClkReqNumber[8]" = "1"
 
+	# RP 3 uses uses CLK SRC 5#
+	register "PcieRpClkSrcNumber[2]" = "5"
+	# RP 4 uses uses CLK SRC 2#
+	register "PcieRpClkSrcNumber[3]" = "2"
+	# RP 5 uses uses CLK SRC 3#
+	register "PcieRpClkSrcNumber[4]" = "3"
+	# RP 6 uses uses CLK SRC 4#
+	register "PcieRpClkSrcNumber[5]" = "4"
+	# RP 9 uses uses CLK SRC 1#
+	register "PcieRpClkSrcNumber[8]" = "1"
 
 	# USB 2.0 Enable all ports
         register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)"		# TYPE-A Port