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authorNaresh G Solanki <naresh.solanki@intel.com>2016-11-06 14:12:55 +0530
committerMartin Roth <martinroth@google.com>2016-11-07 20:54:19 +0100
commitb006a3fe5374e0d7b4b0e6e3dc43a55a8f27410a (patch)
tree13bd994c25c41a9588b92d009855458970948f38 /src/mainboard/intel/kblrvp
parent2413cf3dd16dac52e754dcdbc6513b83dd09e0d6 (diff)
downloadcoreboot-b006a3fe5374e0d7b4b0e6e3dc43a55a8f27410a.tar.xz
mainboard/intel/kblrvp: Configure usb over current pin & cdclock
Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/kblrvp')
-rw-r--r--src/mainboard/intel/kblrvp/ramstage.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index ed37681822..6a509b7b6d 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -18,7 +18,19 @@
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
+ u8 i;
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+ params->CdClock = 3;
+
+ /* Set proper OC for various USB ports*/
+ u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8};
+ u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 };
+
+ for (i = 0; i < ARRAY_SIZE(usb2_oc); i++)
+ params->Usb2OverCurrentPin[i] = usb2_oc[i];
+
+ for (i = 0; i < ARRAY_SIZE(usb3_oc); i++)
+ params->Usb3OverCurrentPin[i] = usb3_oc[i];
}