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authorArchana Patni <archana.patni@intel.com>2015-11-11 01:29:23 +0530
committerMartin Roth <martinroth@google.com>2016-01-17 22:54:17 +0100
commit7846e34c02473a2a000e1fda1e2051475ef3fbf1 (patch)
treedba3417a968fa94dd241cbcd85be65eb5975b9fb /src/mainboard/intel/kunimitsu
parentdf13c31ed6fdad2cdb6e8e874f26e5cad2ce935f (diff)
downloadcoreboot-7846e34c02473a2a000e1fda1e2051475ef3fbf1.tar.xz
intel/skylake: disable heci1 if psf is unlocked
This patch adds support for disabling the heci1 device at the end of boot sequence. Prior to this, FSP would have sent the end of post message to ME and initiated the d0i3 bit. This uses the Psf unlock policy and the p2sb device to disable the heci1 device, then lock the configuration and hide the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu or glados board. set the hecienabled policy to 0 and check for heci 1 device status in kernel lspci. CQ-DEPEND=CL:*238451 Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358 Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311912 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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