skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI

Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 11 insertions, 11 deletions

diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 473d9a06d2..721c74c57a 100644
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -71,7 +71,7 @@ static const struct pad_config gpio_table[] = {
 /* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
 /* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* SD_CD_WAKE */	PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
+/* SD_CD_WAKE */	PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* EC_LPC_CLK */	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
 /* PCH_LPC_CLK */	PAD_CFG_NC(GPP_A10),
@@ -90,7 +90,7 @@ static const struct pad_config gpio_table[] = {
 /* ISH_GP5 */		PAD_CFG_NC(GPP_A23),
 /* CORE_VID0 */ 	PAD_CFG_NC(GPP_B0),
 /* CORE_VID1 */ 	PAD_CFG_NC(GPP_B1),
-/* HSJ_MIC_DET */	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+/* HSJ_MIC_DET */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
 /* TRACKPAD_INT */	PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
 /* BT_RF_KILL */	PAD_CFG_NC(GPP_B4),
 /* SRCCLKREQ0# */	PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
@@ -102,7 +102,7 @@ static const struct pad_config gpio_table[] = {
 /* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
 /* PM_SLP_S0 */  	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* PCH_BUZZER */	PAD_CFG_GPI(GPP_B14, NONE, DEEP),
+/* PCH_BUZZER */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
 /* GSPI0_CS# */ 	PAD_CFG_NC(GPP_B15),
 /* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
 /* SSD_PCIE_WAKE */	PAD_CFG_NC(GPP_B17),
@@ -118,16 +118,16 @@ static const struct pad_config gpio_table[] = {
 /* M2_WWAN_PWREN */	PAD_CFG_NC(GPP_C3),
 /* SML0DATA */		PAD_CFG_NC(GPP_C4),
 /* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
-/* EC_IN_RW */		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+/* EC_IN_RW */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
 /* USB_CTL */		PAD_CFG_NC(GPP_C7),
 /* UART0_RXD */		PAD_CFG_NC(GPP_C8),
 /* UART0_TXD */		PAD_CFG_NC(GPP_C9),
 /* NFC_RST* */		PAD_CFG_NC(GPP_C10),
 /* EN_PP3300_KEPLER */	PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
-/* PCH_MEM_CFG0 */	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
-/* PCH_MEM_CFG1 */	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
-/* PCH_MEM_CFG2 */	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
-/* PCH_MEM_CFG3 */	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+/* PCH_MEM_CFG0 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+/* PCH_MEM_CFG1 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+/* PCH_MEM_CFG2 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+/* PCH_MEM_CFG3 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
@@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
 /* GD_UART2_RXD */	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 /* GD_UART2_TXD */	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 /* TCH_PNL_PWREN */	PAD_CFG_GPO(GPP_C22, 1, DEEP),
-/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* SPI_WP_STATUS */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 /* ITCH_SPI_CS */	PAD_CFG_NC(GPP_D0),
 /* ITCH_SPI_CLK */	PAD_CFG_NC(GPP_D1),
 /* ITCH_SPI_MISO_1 */	PAD_CFG_NC(GPP_D2),
@@ -163,7 +163,7 @@ static const struct pad_config gpio_table[] = {
 /* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
 /* SATAXPCIE1 */	PAD_CFG_NC(GPP_E1),
 /* SSD_PEDET */ 	PAD_CFG_NC(GPP_E2),
-/* AUDIO_DB_ID */	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+/* AUDIO_DB_ID */	PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
 /* SSD_SATA_DEVSLP */	PAD_CFG_NC(GPP_E4),
 /* SATA_DEVSLP1 */	PAD_CFG_NC(GPP_E5),
 /* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6),
@@ -234,7 +234,7 @@ static const struct pad_config gpio_table[] = {
 /* Early pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* SPI_WP_STATUS */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
 };