mainboard/intel/leafhill: initial leafhill board changes

This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.

The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.

Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.

Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18039
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 0 insertions, 51 deletions

diff --git a/src/mainboard/intel/leafhill/chromeos.c b/src/mainboard/intel/leafhill/chromeos.c
deleted file mode 100644
index 256db16548..0000000000
--- a/src/mainboard/intel/leafhill/chromeos.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <baseboard/variants.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
-#include <variant/gpio.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
-		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		{GPIO_EC_IN_RW, ACTIVE_HIGH,
-			gpio_get(GPIO_EC_IN_RW), "EC in RW"},
-	};
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-int get_write_protect_state(void)
-{
-	/* Read PCH_WP GPIO. */
-	return gpio_get(GPIO_PCH_WP);
-}
-
-void mainboard_chromeos_acpi_generate(void)
-{
-	const struct cros_gpio *gpios;
-	size_t num;
-
-	gpios = variant_cros_gpios(&num);
-	chromeos_acpi_gpio_generate(gpios, num);
-}