diff options
author | Brenton Dong <brenton.m.dong@intel.com> | 2017-01-04 15:12:27 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-24 18:00:21 +0100 |
commit | 5f1f0538cf46cea122c49cc103771fd839d24b37 (patch) | |
tree | d0624e13368898997b40be69831d1f1af5d846fe /src/mainboard/intel/leafhill/smihandler.c | |
parent | b46c4ecaba97cc1edbfa2114651fc2bcbf49914b (diff) | |
download | coreboot-5f1f0538cf46cea122c49cc103771fd839d24b37.tar.xz |
mainboard/intel: add leafhill board directory
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18038
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/leafhill/smihandler.c')
-rw-r--r-- | src/mainboard/intel/leafhill/smihandler.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/intel/leafhill/smihandler.c b/src/mainboard/intel/leafhill/smihandler.c new file mode 100644 index 0000000000..fe4f8c4de3 --- /dev/null +++ b/src/mainboard/intel/leafhill/smihandler.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <soc/gpio.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} |