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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:33:48 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:17 +0000 |
commit | 298619f6d9adde49b4279c906b0d20a41f919a61 (patch) | |
tree | 5f69fd9592a077a7b5e35a955bfc2e8b1b5370ea /src/mainboard/intel/littleplains/dsdt.asl | |
parent | bc29bd0de65f1c2054117d42a9e3241ed4c3db80 (diff) | |
download | coreboot-298619f6d9adde49b4279c906b0d20a41f919a61.tar.xz |
mb/*/*: Drop Intel Rangeley mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/mainboard/intel/littleplains/dsdt.asl')
-rw-r--r-- | src/mainboard/intel/littleplains/dsdt.asl | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl deleted file mode 100644 index 4aad8a8b15..0000000000 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Include mainboard configuration - #include <acpi/mainboard.asl> - - // Include debug methods - #include <arch/x86/acpi/debug.asl> - - // Some generic macros - #include <southbridge/intel/common/acpi/platform.asl> - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl> - - #include "acpi/thermal.asl" - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl> - #include <southbridge/intel/fsp_rangeley/acpi/soc.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/common/acpi/sleepstates.asl> -} |