mainboard/intel: Add Little Plains

This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp

Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 49 insertions, 0 deletions

diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl
new file mode 100644
index 0000000000..dbb8b15abf
--- /dev/null
+++ b/src/mainboard/intel/littleplains/dsdt.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Include debug methods
+	#include <arch/x86/acpi/debug.asl>
+
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
+
+	#include "acpi/thermal.asl"
+
+	#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
+			#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
+}