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| author | York Yang <york.yang@intel.com> | 2014-11-25 15:54:08 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-11-29 22:57:50 +0100 |
| commit | 4a91f6443121396b2339b06831249453055e3e24 (patch) | |
| tree | d7d0fa0260aabe9b298adec0ed8c1f99425f8dd4 /src/mainboard/intel/minnowmax/devicetree.cb | |
| parent | 5f19eb6f402e3fa5c095d275f6483cf61edfb59b (diff) | |
| download | coreboot-4a91f6443121396b2339b06831249453055e3e24.tar.xz | |
mainboard/intel/minnowmax: use Baytrail Gold3 FSP
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max
to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use
different FSP image.
Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7581
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax/devicetree.cb')
| -rwxr-xr-x[-rw-r--r--] | src/mainboard/intel/minnowmax/devicetree.cb | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index dd999a09e0..ae11d6a020 100644..100755 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -36,6 +37,23 @@ chip soc/intel/fsp_baytrail register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "11" + register "DIMMtRPtRCD" = "11" + register "DIMMtWR" = "12" + register "DIMMtWTR" = "6" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "6" + register "DIMMtFAW" = "20" device cpu_cluster 0 on device lapic 0 on end |