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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:42:40 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:40:11 +0000 |
| commit | eb5147027e974ba365aa4706935c7c9582cf7619 (patch) | |
| tree | d6ddb25625b91a6db86b7680ca3c92755044a31e /src/mainboard/intel/minnowmax/dsdt.asl | |
| parent | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (diff) | |
| download | coreboot-eb5147027e974ba365aa4706935c7c9582cf7619.tar.xz | |
mb/*/*: Drop FSP_BAYTRAIL support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/minnowmax/dsdt.asl | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl deleted file mode 100644 index bea6af7973..0000000000 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define INCLUDE_LPE 1 -#define INCLUDE_SCC 1 -#define INCLUDE_EHCI 1 -#define INCLUDE_XHCI 1 -#define INCLUDE_LPSS 1 - - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/fsp_baytrail/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/common/acpi/sleepstates.asl> - - #include "acpi/mainboard.asl" -} |