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| author | Martin Roth <gaumless@gmail.com> | 2014-05-21 14:23:12 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-07-30 19:01:20 +0200 |
| commit | 90957f885294527ff9342f56d2e07c5a23fb1ce2 (patch) | |
| tree | d968870ab97604d3582267fabf546af915a21455 /src/mainboard/intel/mohonpeak/dsdt.asl | |
| parent | 829c41da6cd9d8e9c9244c8c9ea2b181ea5ab930 (diff) | |
| download | coreboot-90957f885294527ff9342f56d2e07c5a23fb1ce2.tar.xz | |
mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
Add the Mohon Peak CRB.
Updates to come.
Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6371
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/mohonpeak/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/dsdt.asl | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl new file mode 100644 index 0000000000..297a2b3a53 --- /dev/null +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Include debug methods + #include <arch/x86/acpi/debug.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl> + + #include "acpi/thermal.asl" + + #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl> + #include <southbridge/intel/fsp_rangeley/acpi/soc.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> +} |