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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:33:48 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:17 +0000 |
| commit | 298619f6d9adde49b4279c906b0d20a41f919a61 (patch) | |
| tree | 5f69fd9592a077a7b5e35a955bfc2e8b1b5370ea /src/mainboard/intel/mohonpeak/irqroute.h | |
| parent | bc29bd0de65f1c2054117d42a9e3241ed4c3db80 (diff) | |
| download | coreboot-298619f6d9adde49b4279c906b0d20a41f919a61.tar.xz | |
mb/*/*: Drop Intel Rangeley mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/mainboard/intel/mohonpeak/irqroute.h')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/irqroute.h | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h deleted file mode 100644 index 43a69d9620..0000000000 --- a/src/mainboard/intel/mohonpeak/irqroute.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef IRQROUTE_H -#define IRQROUTE_H - -#include <southbridge/intel/fsp_rangeley/irq.h> -#include <southbridge/intel/fsp_rangeley/pci_devs.h> - -/* - * IR01h PCIe INT(ABCD) - PIRQ ABCD - * IR02h PCIe INT(ABCD) - PIRQ ABCD - * IR03h PCIe INT(ABCD) - PIRQ ABCD - * IR04h PCIe INT(ABCD) - PIRQ ABCD - * IR0Bh IQIA INT(ABCD) - PIRQ EFGH - * IR0Eh RAS INT(A) - PIRQ A - * IR13h SMBUS1 INT(A) - PIRQ B - * IR15h GBE INT(A) - PIRQ CDEF - * IR1Dh EHCI INT(A) - PIRQ G - * IR13h SATA2.0 INT(A) - PIRQ H - * IR13h SATA3.0 INT(A) - PIRQ A - * IR1Fh LPC INT(ABCD) - PIRQ HGBC - */ - - /* Devices set as A, A, A, A evaluate as 0, and don't get set */ -#define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ - PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) - -/* - * Route each PIRQ[A-H] to a PIC IRQ[0-15] - * Reserved: 0, 1, 2, 8, 13 - * PS2 keyboard: 12 - * ACPI/SCI: 9 - * Floppy: 6 - */ -#define PIRQ_PIC_ROUTES \ - PIRQ_PIC(A, 10), \ - PIRQ_PIC(B, 11), \ - PIRQ_PIC(C, 10), \ - PIRQ_PIC(D, 11), \ - PIRQ_PIC(E, 14), \ - PIRQ_PIC(F, 15), \ - PIRQ_PIC(G, 14), \ - PIRQ_PIC(H, 15) - -#endif /* IRQROUTE_H */ |