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| author | Marc Jones <marc.jones@se-eng.com> | 2015-04-22 23:16:31 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-24 00:37:37 +0200 |
| commit | 786879777a70cb82c94588e6d14c8fdd18ab4345 (patch) | |
| tree | a3dea1ee11739a00b63ffead17d7cd29078a70b8 /src/mainboard/intel/mohonpeak | |
| parent | be34797e4c2a5b74bb8fcbbe9e4301b471d185e5 (diff) | |
| download | coreboot-786879777a70cb82c94588e6d14c8fdd18ab4345.tar.xz | |
fsp: Move fsp to fsp1_0
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.
Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/mohonpeak')
| -rw-r--r-- | src/mainboard/intel/mohonpeak/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index e06682ccd8..6218e3848d 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <drivers/intel/fsp/fsp_util.h> +#include <drivers/intel/fsp1_0/fsp_util.h> #include <southbridge/intel/fsp_rangeley/soc.h> #include <southbridge/intel/fsp_rangeley/gpio.h> #include <southbridge/intel/fsp_rangeley/romstage.h> |