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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-08-12 15:00:51 +0000
committerRonald G. Minnich <rminnich@gmail.com>2009-08-12 15:00:51 +0000
commit0588d19abef62dad63a7794a37bdd6a71c526d9e (patch)
tree1c507caa1ffed6ceb73d3e13fc9b766a713d16e2 /src/mainboard/intel/mtarvon
parent38cd29ebd7282333650cf11ed50c7f2fd4031e80 (diff)
downloadcoreboot-0588d19abef62dad63a7794a37bdd6a71c526d9e.tar.xz
Kconfig!
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/mtarvon')
-rw-r--r--src/mainboard/intel/mtarvon/devicetree.cb44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb
new file mode 100644
index 0000000000..1a11859b09
--- /dev/null
+++ b/src/mainboard/intel/mtarvon/devicetree.cb
@@ -0,0 +1,44 @@
+chip northbridge/intel/i3100
+ device pci_domain 0 on
+ device pci 00.0 on end # IMCH
+ device pci 00.1 on end # IMCH error status
+ device pci 01.0 on end # IMCH EDMA engine
+ device pci 02.0 on end # PCIe port A/A0
+ device pci 03.0 on end # PCIe port A1
+ chip southbridge/intel/i3100
+ # PIRQ line -> legacy IRQ mappings
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1c.0 on end # PCIe port B0
+ device pci 1c.1 on end # PCIe port B1
+ device pci 1c.2 on end # PCIe port B2
+ device pci 1c.3 on end # PCIe port B3
+ device pci 1d.0 on end # USB (UHCI) 1
+ device pci 1d.1 on end # USB (UHCI) 2
+ device pci 1d.7 on end # USB (EHCI)
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 on end # audio
+ device pci 1e.3 on end # modem
+ device pci 1f.0 on # LPC bridge
+ chip superio/intel/i3100
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA479M
+ device apic 0 on end
+ end
+ end
+end