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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-22 16:33:24 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-30 10:21:43 +0100
commit773485b8920145443da8b09712553c10c954fed1 (patch)
treefff1c5eec6b6b7782da4d9d8c0afa3492bd583a8 /src/mainboard/intel/mtarvon
parent2b9814629b4b7d96340033fc38c5003e6a8db93e (diff)
downloadcoreboot-773485b8920145443da8b09712553c10c954fed1.tar.xz
intel CAR: Fix DCACHE_RAM_BASE for old sockets
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/mtarvon')
-rw-r--r--src/mainboard/intel/mtarvon/Kconfig8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 4097fa7a23..75bca403f2 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -23,14 +23,6 @@ config IRQ_SLOT_COUNT
int
default 1
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAX_CPUS
int
default 4