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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-15 00:36:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:51:42 +0000
commita64b4f454894988a9c043d53d00b493852f261a3 (patch)
tree44aacf270999724b4461edb3b4c35959482b4330 /src/mainboard/intel/saddlebrook
parentd5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (diff)
downloadcoreboot-a64b4f454894988a9c043d53d00b493852f261a3.tar.xz
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index a25cb8c579..5c64326e3e 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -14,9 +14,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"